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n1106 ms pc b8-6323 no.a0259-1/16 any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications t hat require extremely high levels of re liability, such as life-support systems, aircraft?s control systems, or other applications w hose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before using any sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein. LA79500E overview this LA79500E is a 6-input, 3-output switch for tv. functions ? composite 6 inputs with 3 outputs ? component 2 inputs with 2 outputs ? audio 8 inputs with 3 outputs (l/r) ? serial control with i 2 c bus ? general purpose i/o ? acceptance from y/c comb filter output ? s1, s2 protocol interface ? y/c mix circuit ? all video and audio output gains are selectable by a single bit as 0 or 6db. ? sync-tip clamps include a simple signal detector readable over i 2 c bus. specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max 13 v allowable current electric power pd max * mounted on a board. 1600 mw operating temperature topr -25 to +75 c storage temperature tstg -55 to +150 c * mounted on a board : 114.3 76.1 1.6mm 3 , glass epoxy resin. operating conditions at ta = 25 c parameter symbol conditions ratings unit recommending supply voltage v cc 12 v operating supply voltage v cc op 11.4 to 12.7 v orderin g number : ena0259 monolithic linear ic for tv 6-input, 3-output switch
LA79500E no.a0259-2/16 electrical characteristics/operating conditions at ta = 25 c, v cc = 12v ratings parameter symbol conditions min typ max unit current consumption i cc no signal, no load 67 90 113 ma [video system] frequency response characteristic s frv 100khz/7mhz -1.0 0 1.0 db maximum input level ddv f = 100khz, output thd = 1% input 1.4 1.6 vp-p voltage gain 1 gvv1 6db select 5.9 6.4 6.9 db voltage gain 2 gvv2 0db select 0.0 0.4 0.9 db cross talk vctv f = 3.58mhz -60 -55 db [audio system] voltage gain 1 gva1 6db select 5.9 6.4 6.9 db voltage gain 2 gva2 0db select 0.0 0.4 0.9 db frequency response characteristic s fra 100hz/20khz -1.0 0 1.0 db total harmonic distortion thd f = 1khz, 2.2vp-p input 0.03 0.05 % maximum input level dda f = 1khz, output thd = 0.3% input 2.3 2.5 vrms cross talk vcta f = 1khz, 1vp-p input -90 -80 db supply ripple rejection ratio srrr f = 100hz, 0.3vp-p applied to v cc -55 -40 db s/n ratio s/na f = 1khz, 1vrms input -100 -90 db [logic system] high level input voltage vih 3.5 5.0 v low level input voltage vil 0 1.5 v low level output voltage vol sda 3ma current supplied 0 0.4 v high level input current iih v ih = 4.5v 0 10 a low level input current iil v il = 0.4v 0 10 a maximum clock frequency fscl 0 100 khz minimum waiting time for data change tbuf 4.7 s minimum waiting time for data transfer start thd:sta 4.0 s low level clock pulse width tlow 4.7 s high level clock pulse width thigh 4.0 s minimum waiting time for start preparation tsu:sta 4.7 s minimum data hold time thd:dat 0 s minimum data preparation time tsu:dat 250 ns rise time tr 1 s fall time tf 300 ns minimum waiting time for stop preparation tsu:sto 4.7 s gpio1/2/3/4/5/6 (pin5/13/27/33/55/63) high level input voltage gpih 3.5 v low level input voltage gpil 1.5 v high level output voltage gpoh 50 a current loaded 4.0 v low level output voltage gpol 1ma current supplied 1.0 v dc_out (pin67) high level output voltage dcoh dc_out (bus write) 11 r l =100k ? 4.0 4.5 v middle level output voltage dco m dc_out (bus write) 10 r l =100k ? 1.4 1.9 2.4 v low level output voltage dcol dc_out (bus write) 01/00 r l =100k ? 0.5 v dc_in (pin66) high level input voltage dcih dc_in (bus read) 10 3.0 v middle level input voltage dcim dc_in (bus read) 01 1.5 1.9 2.3 v low level input voltage dcil dc_in (bus read) 00 1.0 v
LA79500E no.a0259-3/16 terminal voltage/ input impedance ratings parameter symbol conditions min typ max unit video signal inputs terminal voltage (pin6/14/34/71/75/78) cvyiv 2.0 2.5 3.0 v video signal outputs terminal voltage (pin46/56/64) cvyov 2.0 2.5 3.0 v y signal inputs terminal voltage (pin8/16/21/28/36/80/65) yiv 2.0 2.5 3.0 v y/v signal outputs terminal voltage (pin54/62) yov 2.0 2.5 3.0 v c signal inputs terminal voltage (pin2/10/18/38/68) civ 2.3 2.8 3.3 v c signal outputs terminal voltage (pin52/60) cov 2.3 2.8 3.3 v c signal inputs terminal impedance (pin2/10/18/38/68) ciz 8.0 10.0 12.0 k ? pb/pr signal inputs terminal voltage (pin23/25/30/32) pbriv 2.0 2.5 3.0 v pb/pr signal outputs terminal voltage (pin49/50/57/58) pbrov 1.9 2.4 2.9 v audio signal inputs terminal voltage (pin1/7/9/15/17/22/24/29/31 /35/37/70/72/74/76/79) aiv 5.3 5.8 6.3 v audio signal outputs terminal voltage (pin45/47/51/53/59/61) aov 4.7 5.2 5.7 v audio signal inputs terminal impedance (pin1/7/9/15/17/22/24/29/31 /35/37/70/72/74/76/79) aiz 40.0 50.0 60.0 k ?
LA79500E no.a0259-4/16 package dimensions unit : mm 3174a block diagram 20.0 23.2 0.15 0.35 0.8 (2.7) 3.0max 0.1 0.8 (0.8) 24 1 14.0 17.2 25 40 41 64 65 80 sanyo : qip80e(14x20)
LA79500E no.a0259-5/16 pin description pin no. symbol pin voltage (v) description equivalent circuit 71 75 78 6 14 34 tv1 tv2 cv1 cv2 cv3 cv4 2.5 video signal inputs. input composite video signals. 80 8 16 36 21 28 y1 y2 y3 y4 y5 y6 2.5 y/c separation signal inputs. input luminance signals. 2 10 18 38 c1 c2 c3 c4 2.8 y/c separation signal inputs. input chrominance signals. 70, 72 74, 76 79, 1 7, 9 15, 17 35, 37 22, 24 29, 31 tv1l, tv1r tv2l, tv2r v1l, v1r v2l, v2r v3l, v3r v4l, v4r cp5l, cp5r cp6l, cp6r 5.8 audio signal inputs. 25 23 32 30 pr5 pb5 pr6 pb6 2.5 component pb/pr inputs. 64 56 46 vout1 vout2 vout3 2.5 video signal outputs. output composite video signals. continued on next page.
LA79500E no.a0259-6/16 continued from preceding page. pin no. symbol pin voltage (v) description equivalent circuit 62 54 y/vout1 y/vout2 2.5 video signal outputs. either composite video signal output or luminance signal output can be selected by i 2 c bus control. 60 52 cout1 cout2 2.8 video signal outputs. output chorominance signals. 61 53 47 59 51 45 lout1 lout2 lout3 rout1 rout2 rout3 5.2 audio signal outputs. 4 12 20 40 s-1 s-2 s-3 s-4 composite video/s selector. the detection results are written to the status register. s signal at 3.5v or less. composite video signal at 3.5v or more. this pin is pulled up to 5v by a 100k ? resistor, so the composite video signalis selected when open. 3 11 19 39 s2-1 s2-2 s2-3 s2-4 detects the s2-compatible dc superimposed onto the c signal. 4:3 video signal at 1.3v or less. 4:3 letter-box signal at 1.3v or moreto2.5v or less. 16:9 picture squeezed signal at 2.5v or more. this pin is pulled down to gnd by a 100k ? resistor, so the 4:3 video signal is selected when open. 57 58 49 50 prout1 pbout1 prout2 pbout2 2.4 component pb/pr outputs. continued on next page.
LA79500E no.a0259-7/16 continued from preceding page. pin no. symbol pin voltage (v) description equivalent circuit 5 13 27 33 55 63 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 general purpose i/o. 65 ycomb 2.5 the ycomb pin inputs the signal obtained by y/c separating the vout1 pin output. 68 ccomb 2.8 the ccomb pin inputs the signal obtained by y/c separating the vout1 pin output. 41 adr selects the slave address for the i 2 c bus. 90h at 1.5v or less. 92h at 2.5v or more. 90h when open. 43 data i 2 c bus signal input v il max = 1.5v v ih min = 3.0v v ol max = 0.4v 42 clk i 2 c bus signal input v il max = 1.5v v ih min = 3.0v continued on next page.
LA79500E no.a0259-8/16 continued from preceding page. pin no. symbol pin voltage (v) description equivalent circuit 77 bias 10.2 internal reference bias. connect to gnd via a capacitor. 66 dc_in detection pin of dc input 1.3v or less : 00 1.3v or more to 2.5v or less : 01 2.5v or more : 10 this pin is pulled down to gnd by a 100k ? resistor. 67 dc_out outputs the s2-compatible dc. control is perfomed by the i 2 c bus. s2 protocol output impedance of 103kohm is realized by attaching external resisitance of 4.7kohm. dc_out (bus) output dc 00 0v 01 0v 10 1.9v 11 4.5v 48 mute all signal output mute. mute off at 1.5v or less mute on at 2.0v or more. mute off when open. 26 v cc 12.0 v cc 44 73 gnd 0.0 gnd 69 nc not connected
LA79500E no.a0259-9/16 serial control specification slave address msb lsb 1 0 0 1 0 0 adr r/w adr : this bit sets the slave address set by the address pin. 0 : address pin ?low? 1 : address pin ?high? r/w : read/write mode 0 : control data write 1 : staus register read data format (write mode) s slave address (8bit) a sub address (8bit) a data address (8bit) 00 to 05 group a p ? ? ? start condition acknowledge stop condition sub address and data byte write mode * : indicates undefined sub address data byte (underline is initial setting.) msb lsb d8 d7 d6 d5 d4 d3 d2 d1 00 (0000 0000) vout1 gain 0 : 0db 1 : 6db vout1 000 : tv1 100 : cv3 001 : tv2 101 : cv4 010 : cv1 110 : mute 011 : cv2 111 : mute l/rout1 000 : tv1 100 : v3 001 : tv2 101 : v4 010 : v1 110 : mute 011 : v2 111 : pr/pb l/rout1 gain 0 : 0db 1 : 6db 01 (0000 0001) vout2 gain 0 : 0db 1 : 6db vout2 000 : tv1 100 : cv3 001 : tv2 101 : cv4 010 : cv1 110 : mute 011 : cv2 111 : y+c l/rout2 000 : tv1 100 : v3 001 : tv2 101 : v4 010 : v1 110 : mute 011 : v2 111 : pr/pb l/rout2 gain 0 : 0db 1 : 6db 02 (0000 0010) vout3 gain 0 : 0db 1 : 6db vout3 000 : tv1 100 : cv3 001 : tv2 101 : cv4 010 : cv1 110 : mute 011 : cv2 111 : y+c l/rout3 000 : tv1 100 : v3 001 : tv2 101 : v4 010 : v1 110 : mute 011 : v2 111 : pr/pb l/rout3 gain 0 : 0db 1 : 6db 03 (0000 0011) * vout3 y+c 00 : y1/c1 01 : y2/c2 10 : y3/c3 11 : y4/c4 * l/rout1 0 : pr5/pb5 1 : pr6/pb6 l/rout2 0 : pr5/pb5 1 : pr6/pb6 l/rout3 0 : pr5/pb5 1 : pr6/pb6 * 04 (0000 0100) y/cout1 gain 0 : 0db 1 : 6db y/c/pr/pbout1 000 : y1/c1 100 : y/ccomb 001 : y2/c2 101 : y5/pr5/pb5 010 : y3/c3 110 : y6/pr6/pb6 011 : y4/c4 111 : mute gpo1 0 : low 1 : high gpo2 0 : low 1 : high gpo3 0 : low 1 : high gpo4 0 : low 1 : high 05 (0000 0101) y/cout2 gain 0 : 0db 1 : 6db y/c/pr/pbout2 & vout2 y+c 000 : y1/c1 100 : vout2 001 : y2/c2 101 : y5/pr5/pb5 010 : y3/c3 110 : y6/pr6/pb6 011 : y4/c4 111 : mute gpo5 0 : low 1 : high gpo6 0 : low 1 : high dc_out 00 /01 : 0v (low) 10 : 1.9v (mid) 11 : 4.5v (high)
LA79500E no.a0259-10/16 vout1/2/3 gain : vout1/2/3 output gain selector 0 : 0db output 1 : 6db output y/cout1/2 : y/vout1/2 and cout1/2, pr/pbout1/2 output gain selector 0 : 0db output 1 : 6db output l/rout1/2/3 gain : lout1/2/3 and rout1/2/3 output gain selector 0 : 0db output 1 : 6db output vout1/2/3 : these bits select the input signals output to each video output 0 : selects the tv1 input 4 : selects the cv3 input 1 : selects the tv2 input 5 : selects the cv4 input 2 : selects the cv1 input 6 : mute 3 : selects the cv2 input 7 : mute (vout1), y+c (vout2 / 3) (vout2:set *2) l/rout1/2/3(1) : these bits select the input signals output to each audio l/r output 0 : selects the tv1l/r input 4 : selects the v3l/r input 1 : selects the tv2l/r input 5 : selects the v4l/r input 2 : selects the v1l/r input 6 : mute 3 : selects the v2l/r input 7 : selects the pr/pb (cr/cb) mode *1 *1 l/rout1/2/3(2) : this bit selects the input signals output to cp5l/r, cp6l/r output 0 : selects the cp5l/r input 1 : selects the cp6l/r input vout3 y+c : these bits select the y+c input signals output to vout3 (y+c mode) 0 : selects the y1/c1 input 2 : selects the y3/c3 input 1 : selects the y2/c2 input 3 : selects the y4/c4 input *2 y/c/pr/pbout1/2 & vout2 y+c : these bits select the input signals output to each video output 0 : selects the y1/c1 input 4 : selects the y/ccomb input, vout2 output 1 : selects the y2/c2 input 5 : selects the y5/pr5/pb5 input 2 : selects the y3/c3 input 6 : selects the y6/pr6/pb6 input 3 : selects the y4/c4 input 7 : mute gpo1/2/3/4/5/6 : this bit set the output from gpio1/2/3/4/5/6 0 : low(1.0v or less) 1 : high(4.0v or more) dc_out : these bits set the dc voltage output from pin67 (dc_out) 0 : 0v 2 : 1.9v 1 : 0v 3 : 4.5v
LA79500E no.a0259-11/16 data format (read mode) s slave address (8bit) a data1 (8bit) a data2 (8bit) a data3 (8bit) a data4 (8bit) a data5 (8bit) ap ? ? ? start condition acknowledge stop condition read mode * : indicates undefined data byte msb lsb d8 d7 d6 d5 d4 d3 d2 d1 data1 tv1 0 : no sig. 1 : signal tv2 0 : no sig. 1 : signal cv1 0 : no sig. 1 : signal cv2 0 : no sig. 1 : signal cv3 0 : no sig. 1 : signal cv4 0 : no sig. 1 : signal * * data2 ycomb 0 : no sig. 1 : signal y1 0 : no sig. 1 : signal y2 0 : no sig. 1 : signal y3 0 : no sig. 1 : signal y4 0 : no sig. 1 : signal y5 0 : no sig. 1 : signal y6 0 : no sig. 1 : signal * data3 gpi1 0 : low 1 : high gpi2 0 : low 1 : high gpi3 0 : low 1 : high gpi4 0 : low 1 : high gpi5 0 : low 1 : high gpi6 0 : low 1 : high dc_in 00 : 1.3v or less 01 : 1.3v or more to 2.5v or less 10 : 2.5v or more data4 s-1 sel 1 : low 0 : high s-2 sel 1 : low 0 : high s-3 sel 1 : low 0 : high s-4 sel 1 : low 0 : high * * * * data5 s2-1 00 : 4:3 video sig. 01 : 4:3 letter-box 10 : 16:9 11 : no sig. s2-2 00 : 4:3 video sig. 01 : 4:3 letter-box 10 : 16:9 11 : no sig. s2-3 00 : 4:3 video sig. 01 : 4:3 letter-box 10 : 16:9 11 : no sig. s2-4 00 : 4:3 video sig. 01 : 4:3 letter-box 10 : 16:9 11 : no sig. s-1 sel to s-4 sel 1 : s-1 to s-4 pins are grounded. 0 : s-1 to s-4 pins are not grounded. s2-1 to s2-4 s2-1 to s2-4 are actually determined by comparing the s2-1 to s2-4 pin dc voltages with two threshold. however, when the s-1 to s-4 pins are open(high) the outputs are fixed to ?11?. s2-1 to s2-4 : data bit 1.3v or less : 00 1.3v or more to 2.5v or less : 01 2.5v or more : 10 s-1 to s-4 open (high) : 11
LA79500E no.a0259-12/16 1) data transfer manual : [1] is high level. [0] is low level. i 2 c-bus control system is adopted in sw lsi and sw lsi is controlled by scl (serial clock) and sda (serial data). at first, please set up the start condition *1 by these two terminals (scl and sda). and next, please input the 8bits data which should be synchronized with scl into sda terminal still more, please give priority to high rank bit at data transfer order (msb lsb). the 9th bit is called as ack (ac knowledge), sw lsi sends [0] to the sda terminal during scl [1] period. so, please open the port of micro-processor during this period. and next, please transfer sub-address data (calle d as group) and control data. as t hus the data transfer stop condition *2 is finished. *1 : sda rise up during sci is [1] *2 : sda fall down during scl is [1] 2) transfer data format the transfer data is composed by start condition , slav e address data, sub- address data, control data and stop condition. there are 6 control groups. after setting up the start condition, please transfer the sl ave address. sub-address data and next control data (please see the fig.1) slave address is composed by 7bits, and this bit 8th bit should be set as [0] at write mode and [1] at read mode. this 8th bit called as r/w bit, and this bit shows the data transmission direction. [0] means send mode (accept mode with sw lsi) an d [1] means accept mode (send mode with sw lsi) fundamentally. the both of sub-address data and control data are composed by 8bits, and the one control action is defined with combination of these two data. and if you want to control 2 or more groups at the same mode, you can realize it by sending some control data together. the data makes meaning with all bits, so you cannot stop the sending until all data transfer is over. if you want to stop transfer action, please transfer the stop condition. you can select how to send as follws.(write mode) pattern a start condition + slave address + sub address 00 + data 00 + data 01 + data 02 + data 03 + data 04 + data 05 + stop condition pattern b start condition + slave address + sub address 01 + data 01 + data 02 + data 03 + data 04 + data 05 + stop condition pattern c start condition + slave address + sub address 02 + data 02 + data 03 + data 04 + data 05 + stop condition pattern d start condition + slave address + sub address 03 + data 03 + data 04 + data 05 + stop condition pattern e start condition + slave address + sub address 04 + data 04 + data 05 + stop condition pattern f start condition + slave address + sub a ddress (01 or 02 or 03 or 04 or 05) + data (01 or 02 or 03 or 04 or 05) + stop condition (send only 1data) start condition slave address r/w ac k sub-address ack control data ack ... stop condition fig.1 data structure
LA79500E no.a0259-13/16 3) initialize sw lsi is initialized as the following mode for ci rcuit protection. please see ?serial control table?. characteristics of the sda and scl 1/0 stages for sw lsi ratings parameter symbol min max unit low level input voltage vil 0 1.5 v high level input voltage vih 3.5 5.0 v low level output current iol 3.0 ma scl clock frequency fscl 100 khz set-up time for a repeated start condition tsu:sta 4.7 s hold time start condition. after this period, t he first clock pulse is generated. thd:sta 4.0 s low period of the scl clock tlow 4.7 s rise time of both sda and sdl signals tr 0 1.0 s high period of the scl clock thigh 4.0 s fall time of both sda and sdl signals tf 0 1.0 s data hold time thd:dat 0 s data set-up time tsu:dat 250 ns set-up time for stop condition tsu:sto 4.0 s bus fred time between a stop and start condition tbuf 4.7 s fig.2 definition of timing
LA79500E no.a0259-14/16 video block
LA79500E no.a0259-15/16 audio block
LA79500E ps no.a0259-16/16 test circuit ? specifications of any and all sanyo semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described pr oducts in the independent state, and are not guarantees of the performance, characteri stics, and functions of the described products as mounted in the customer's products or equipmen t. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. ? sanyo semiconductor co., ltd. strives to supply hi gh-quality high-reliability products. however, any and all semiconductor products fail with some probabilit y. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other proper ty. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measur es include but are not limited to protective circuits and error prevention circuits fo r safe design, redundant desi gn, and structural design. ? in the event that any or all sanyo semiconductor products (including technical data, services) described or contained herein are controlled under any of applicab le local export control laws and regulations, such products must not be exported without obtaining t he export license from the authorities concerned in accordance with the above law. ? no part of this publication may be reproduced or tr ansmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, of otherwise, without the prior written pe rmission of sanyo semiconductor co., ltd. ? any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "d elivery specification" for the sanyo semiconductor prod uct that you intend to use. ? information (including circuit diag rams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo semiconductor believes information herein is accurate and reliable, but no guarantees are made or imp lied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of november, 2006. specifications and inform ation herein are subject to change without notice.

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